The present invention relates to the field of molded case integrated circuits and especially to integrated circuits with a molded case comprising a device for reducing the dynamic impedance of power lines.
When operating, some integrated circuits require high current peaks. It is then necessary that the supply lines have low dynamic impedances, that is, that these lines each have a low resistance and a low inductance and are provided with a decoupling capacity coupled to another supply line.
According to conventional bonding techniques, a method for decreasing resistances and inductances of connections is to increase the number of connections affected to supply voltages. Thus, the parasitic resistances and inductances are paralleled and their values are practically divided by the number of connections in parallel. But, if it is desired to sufficiently decrease the parasitic resistances and inductances, the number of connections affected to the power supplies must be substantially increased, which is incompatible with integrated circuits requiring a large number of inputs/outputs.
In the description that follows, the plane of the connection leads will be referred to as connection network.
FIGS. 1A and 1B are top and cross-section views, respectively, of a multilayer lead frame of the prior art adapted to the lead frame and wire bonding technique. This lead frame comprises several layers constituted by a layer of leads or connection network 10, a first metal plane 11 and a second metal plane 12, separated and bonded by insulating films 13 and 14. Plane 12 supports a chip 15. Plane 11 is annular to leave space around chip 15 for connecting it to plane 12. Legs 16 on the periphery of plane 11 are soldered on leads connected to a first supply terminal. Similarly, legs 17 on the periphery of plane 12 are soldered to other leads connected to a second supply terminal. The supply pads of chip 15 normally intended to be connected to the supply leads, are bonded by wires to the corresponding planes and the remaining pads are bonded by wires to the proximal ends of the remaining leads.
Thus, the supply connections pass through planes instead of passing through long thin leads. This substantially decreases parasitic resistances and inductances. Moreover, planes 11 and 12 form a decoupling capacity between the supply lines.
However, compared to a realization comprising only one layer corresponding to the connection network 10, with this arrangement, it is necessary to shorten the ends of the leads in order to be able to bond the chip supply pads to the planes. This involves the use of longer wires between the other chip pads and the ends of the leads. In practice, three layers is a maximum because, otherwise, the bonding wires between the chip and the ends of the leads would be too long to ensure a satisfactory reliability and, especially, this would introduce additional resistances and inductances, which is precisely what is desired to avoid.
A further drawback of this arrangement is that wires are particularly difficult to solder on the proximal ends of the leads because the insulating film 13 which supports them softens under the soldering heat.
Moreover, these multilayer lead frames are expensive since it is necessary to stamp the metal planes 11 and 12 with a specific equipment and their implementation is delicate and requires an adaptation of the conventional processes for handling and soldering the conventional frames, since the bonding wires are of different lengths.